20 Guidelines for Xilinx FPGA Design

LookUp Technology Solutions | March 9th, 2016

  1 FPGA designs are predictable and glitch free when used with Synchronous flops.   2 Use OneHot Encoding for FPGA state machines (FSMs) as FPGA is flop rich. It will speed up your design as well.   3 Use Block RAM for bigger memories ( Arrays above 256 bits )   4 Use distributed RAM  ( LUTRAM ) for smaller memories. (Arrays


Reset Techniques for ASIC and FPGA designs

LookUp Technology Solutions | March 5th, 2016

  Primary purpose of reset is to force the design in to a known state. Real world reset or power-on-reset are asynchronous. But the design world uses flip-flops with two types of resets.    Synchronous Resets: Synchronous resets make sure your design is 100% synchronous. It removes the metastability problem with the assertion or de-assertion of reset. For FPGA designs, synch


How to select Synchronizer for your Design ?

LookUp Technology Solutions | March 3rd, 2016



System Synchronous Clocking vs. Source Synchronous Clocking

LookUp Technology Solutions | March 3rd, 2016

source Hold
  Based on the direction of clock and data, synchronous systems are categorized in to two as source synchronous and system synchronous. System architects plan the clocking of the system first by considering placement of different blocks, Fmax and ease of timing closure. Understanding these two types of clocking will help you in deciding which type of clocking approach to choose for your ne


Asynchronous Cross Clock Domain Data Transfer Techniques

LookUp Technology Solutions | March 3rd, 2016

It is an interesting topic. When we hear about the word “asynchronous”, we think about clocks with different frequency and take care of them with special attention. But, Clocks with same frequency and different phase (or unknown phase) also need the same care from the designers. A term “Clock Domain Crossing” (CDC) has been used frequently in Semiconductor industry when data move from one

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